VERILOG ASIC Design

We have used Verilog extensivley to write RTL code for ASIC designs of all sizes. In addition, Verilog testbenches have been used to perform verification functions. Our synthesis expertise allows us to write compact code that is easily synthesizable.

VHDL ASIC Design

VHDL has also been used extensively to write RTL code for ASIC designs of all sizes. In addition, VHDL testbenches have been used to perform system level verification. Here too, our synthesis expertise allows us to write compact code. This is most appreciated in big ASIC designs or FPGA designs.

FPGA Design

Altera, Xilinx and Actel are a few of the vendors we have worked with for FPGA designs. Tools from these vendors as well as Synopsys FPGA Express has been used to synthesize the designs. If your production volume is high, A great cost savings can be achieved by taking your existing FPGA and converting it into an ASIC.

SYNTHESIS

We have extensive knowledge of the Synopsys tools and have assisted numerous clients in synthesising their designs. We are intimately familiar with LSI, IBM, Fujitsu, Hitachi, NEC, Toshiba, SMOS, TSMC to name a few. As always, each vendor has it's own bag of tricks for efficient synthesis, what cells to use and what not to use. We can help you go thru the synthesis process quickly and painlessly.

ATPG & Other BACKEND

What's an ASIC without all the backend fun stuff. Since each vendor has different requirement, here's an area an expert help could be most appreciated. We can help you with the process as well as generating the proper vectors for sign off and production runs.

SPICE and IBIS Modeling

Our analog experts can assist you in selecting which I/O buffers you should choose for your particular design and technology. Most firms spend an enormous amount of effort designing, verifying, synthesizing, and verifying more gate level logic, and yet there are signal integrity problems in the lab. Here's an area where a bit of work upfront can save a lot of headaches later.